1. Field of the Invention
The present invention relates to a solid-state imaging device and an imaging apparatus. Also, the present invention relates to an imaging apparatus and a camera, which include an imaging device such as a CCD (Charge Coupled Device), CMOS (Complementary Metal Oxide Semiconductor) sensors and so forth.
2. Description of the Related Art
As digital cameras have come into widespread use in recent years, high resolution has come to be demanded even of lower-priced cameras. Also, there has been demand for high resolution not only in digital cameras, but also video cameras, cameras for cellular phones, and so forth. In general, the optical size (outer size of the solid-state imaging device) has not changed, so increase in the number of pixels is synonymous with microfabrication of pixels.
Microfabrication of a pixel is directly linked with reduction in the number of photons entering into a pixel, leading to deterioration of absolute sensitivity which cannot be compensated for with improvement in quantum efficiency. This holds true for both CCD image sensors and CMOS image sensors. However, in general, it is difficult for a CMOS image sensor to condense light since metal wiring is high (thick), and sensitivity is accordingly low.
In light of the above, a technique has been proposed wherein sensitivity is increased while suppressing the deterioration of resolution from the perspective of image processing. The technique thereof will be described with reference to FIG. 30.
As shown in FIG. 30, it is known that with a so-called honeycomb pixel array, each pixel 111 is made up of a slanted square pixel array, whereby the deterioration of space resolution in the vertical and horizontal directions can be suppressed even with a half of the real number of pixels. The number of pixels can be reduced into a half with the same valid pixel region, so the area per unit pixel increases, and accordingly, sensitivity can be improved. There are many lines in the vertical and horizontal directions with artificial space, and pixel data is represented with XY coordinates, so the space resolution of these two axes is important for the perception of resolution, and accordingly, it can be said that a honeycomb pixel array has high sensitivity in many situations.
However, a honeycomb pixel array is a pixel array unsuitable for being integrated. In general, pixel data is a data array with two axes of vertical and horizontal axes, and a pixel of a square grid image sensor is also an array in accordance therewith. Along with this, control (driving and readout) is also performed in the vertical direction and the horizontal direction. On the other hand, with a honeycomb pixel array, a pixel is made up of a slanted square grid, and consequently, the array of control pixels is in a zigzag pattern.
For example, with a CMOS image sensor, in the case of a common square grid pixel array, wiring can be performed effectively by changing each metal wiring layer of the axes in the vertical and horizontal directions. On the other hand, with a honeycomb pixel array, the pixel of the adjacent row or the adjacent column is inserted between pixels in the same row or the same column, so it is unavoidable to dispose wiring in a zigzag manner, which sometimes makes it difficult to connect to a component such as a transistor or the like formed on the silicon surface at a portion overlapped with wiring.
There is a problem in that a honeycomb pixel array is high in wiring density. Accordingly, it is necessary to keep a metal opening large by reducing the number of wiring. Therefore, it is effective to share a pixel transistor (see Japanese Unexamined Patent Application Publication No. 2004-128193).
However, with the technique disclosed in Japanese Unexamined Patent Application Publication No. 2004-128193, it is unavoidable to subject the property of a fine pixel to deterioration. That is to say, with the technique disclosed in Japanese Unexamined Patent Application Publication No. 2004-128193, as shown in FIG. 31A, a transfer gate TG of a charge-to-voltage conversion unit is disposed in a side portion of a pixel 111, which excels in readout property, but includes a problem in that the condensing spot area is compressed. Also, even if a shared portion of a floating diffusion FD serving as a charge-to-voltage conversion unit is disposed between pixels, sharing a pixel transistor between two pixels makes it difficult to sufficiently secure a photodiode PD area.
Also, with a pixel group wherein multiple pixels are arrayed in a two-dimensional square, as shown in FIG. 31B, a floating diffusion FD serving as a charge-to-voltage conversion unit to be shared is disposed at a corner of the pixel 111 via the transfer gate TG. Between two pixels obliquely adjacent to each other, the distance from the condensing center of the pixel 111 thereof to the transfer gate TG can be separated by disposing the transfer gate TG at the corner of the pixel 111 thereof, thereby suppressing deterioration of sensitivity caused by the transfer gate TG absorbing light.
A CMOS imaging apparatus employing a CMOS (Complementary Metal Oxide Semiconductor) is employed as an imaging device such as a camera or the like, and includes a function such as partial readout which is difficult for a CCD (Charge Coupled Device) imaging apparatus, which is advantageous for low power consumption and reduction in size of an imaging apparatus.
In recent years, there has been demand for increase in the number of pixels in a CMOS imaging apparatus. However, a CMOS imaging apparatus includes within a pixel many driver elements such as a photodiode, a transfer transistor, a reset transistor, an amplification transistor, a select transistor, and so forth, so it is difficult to reduce the size of the pixel. Also, the driving load of a pixel circuit and the readout load of a signal from a pixel circuit are increased due to increase in the number of pixels, which has caused a disadvantageous situation for high-speed driving.
One solution to this problem is reduction in load by sharing a transistor. For example, with an arrangement wherein one amplification transistor is shared by multiple photodiodes and transfer transistors, the number of elements can be reduced, such as an amplification transistor to be connected to a vertical signal line, and so forth, whereby the load of the vertical signal line can be reduced at the time of readout of an output signal. Further, a method has been proposed wherein improvement in image quality of an output signal is realized by sharing a photoelectric conversion unit (see Japanese Unexamined Patent Application Publication No. 2006-54276).
Also, one solution relating to microfabrication of a pixel is a method wherein a transistor within a pixel is shared, the number of transistors per one pixel is reduced, and the size of the pixel is reduced (e.g., see Japanese Unexamined Patent Application Publication No. 2001-298177). For example, an arrangement is made wherein a transfer transistor is disposed as to each of multiple photodiodes, and a select transistor, a reset transistor, and an amplification transistor are shared as to the multiple photodiodes and transfer transistors.
In the event of not sharing a transistor, four transistors per pixel are provided in general, but on the other hand, upon four pixels sharing three transistors, the number of transistors can be reduced to 1.75 per pixel. Note that there is an arrangement including no select transistor, depending on the transistor driving method, etc. (see Japanese Unexamined Patent Application Publication No. 2006-54276).